Dolby Digital SR-D optical codes reverse engineering

This is a draft ! Patent: US5710752A

Thanks to the creator of the Gugusse roller for providing a capture of raw codes.

DA-20 decoder teardown

Standard rack-mount decoder for SR-D tracks. Takes video of the scrolling codes from a fast 512x1 CCD sensor (called soundhead) and outputs 6 analog audio channels along with some control signals for the cinema processor thing.
Installation and user manual available on film-tech.com. This website is AWESOME.

CAT. NO. 670

Video processing, analog filtering, analog to digital conversion, small FIFO.

• MAX453: Dual-input multiplexer and video amplifier
• 1513-50A: Fixed delay line 50ohm 50ns
• AD829: High speed, low noise video amplifier
• OPA603: High speed, high voltage amplifier
• TL072: Double FET-input amplifier
• LM311: Comparator
• TL074: Quad FET-input amplifier
• 74LS628: VCO
• AS7C256: 32k * 8 SRAM
• Altera CPLDs
• DS26C31 / P9818: Quad differential line driver
• MP8785AN: 8-bit high speed ADC

CAT. NO. 671

Two of these are used for a total of 4 video processing DSP blocks.

Video digital processing, data extraction from the 2D codes. Each DSP has a small bootloader ROM for configuration by the master DSP56002.
Each DSP has 128k x 24 work RAM.

• DSP56001
• 27C512: 64k * 8 EPROM
• 74HC4538: Dual precision monostables (watchogs ?)
• Altera CPLD
• AS7C1024: 128k * 8 SRAM
• AS7C256: 32k * 8 SRAM

CAT. NO. 673A

Master controller, PLL for film speed tracking, Reed-Solomon EDC, uploading of programs to DSP boards, RS-232 external comm.

• DSP56002
• MX7245: 12-bit DAC
• VCO under a metal shield
• 29C010: 128k * 8 flash memory
• AS7C1024: 128k * 8 SRAM
• AS7C256: 32k * 8 SRAM
• AHA4011B: Reed-Solomon ERC ASIC
• 74HC4538: Dual precision monostables (watchdog ?)
• MAX232: Dual RS-232 driver/receiver

CAT. NO. 675A

AC-3 decoding. The Zoran chip has an embedded CPU of unknown architecture, ROM is external.

• ZR38500: 6-channel AC-3 decoder
• PC16550: UART FIFO
• AS7C256: 32k * 8 SRAM

CAT. NO. 686

Audio DACs for final output. Linear voltage regulators.

• CS4328: Dual 18-bit audio DAC
• NE5532: Dual low noise amplifier
• LM317T: Adjustable voltage regulator

CAT. NO. 611A

Cinema processor, user configuration interface, digital/analog audio switch.

• NE5532: Dual low noise amplifier
• AS7C256: 32k * 8 SRAM
• MCU
• MIC5801: 8-bit high voltage latch
• LM324: Quad op-amp
• MC33078: Dual high speed op-amp

2D code format

Dolby calls the transparent or opaque dots "fixels" for "film pixels".

Total: 76*76 fixels
Four 8*8 fixels corner markers (7-bit 2D Barker codes to find them with autocorrelation)
A center 12*12 fixels logo
= 76*76 - 4*8*8 - 12*12 = 5776 - 400 = 5376 data bits

Four codes per frame at 24 frames per second:
4 * 24 * 5376 = 516096 bps = 504kbps = 63kB/s

Bytes are packed in 2*4 fixel blocks, bit 0 top to bottom, left to right.

Seems to be a 1-out-of-3 interleave.

Raw ASCII data with no interleave: "DOLBY SR*D".
Special code every 44 codes = 11 frames = slightly less than half a second ?

Firmware

Flash contains all "applications" for the DSPs.

Stuck into IDA without knowing the memory map. Found the hard way that the entry point is at $4000, which isn't standard and doesn't match any startup mode of the DSP56002. So something on the PCB such as the Altera CPLD is mapping $4000 at $0000.

32kB bank switching done via the 2 lower bits of PORT D. Bank appears at $6000+.

Work RAM at $3900+, probably starts below.