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Introduction
Master clock
Générateur de fréquence
Régler le volume
PWM
Générateur de bruit
Dent de scie et triangle
Sinus
Interface CPU
Silicium: Volume
Silicum: DAC

Autre forme d'onde: sinus

Todo...

Sinus: LUT de 1/4 période + inversion H/V

Difference avec le triangle:

soundchip

32 STEPs sinus: 1/4 = LUT 8
0~7: LUT[x] (0.5~1): LUT[x]
8~15: LUT[7-x] (1~0.5): LUT[~x]
16~23: 0.5-LUT[x] (0.5~0): ~LUT[x]
24~31: 0.5-LUT[7-x] (0~0.5): ~LUT[~x]

OUT = LUT[STEP[2:0] ^ STEP[3]] ^ STEP[4]

Todo: LUTDATA et OUT en hexa:

soundchip

reg [4:0] STEP;
wire [2:0] LUTADDR;
reg [3:0] LUTDATA;
wire [3:0] OUT;

always @(*)
begin
	case (LUTADDR)
		0: LUTDATA <= 9;	// Un quadrant
		1: LUTDATA <= 11;
		2: LUTDATA <= 12;
		3: LUTDATA <= 13;
		4: LUTDATA <= 14;
		5: LUTDATA <= 14;
		6: LUTDATA <= 15;
		7: LUTDATA <= 15;
	endcase
end

assign LUTADDR = STEP[3] ? ~STEP[2:0] : STEP[2:0];
assign OUT = STEP[4] ? ~LUTDATA : LUTDATA;

Reset et module:

module channel(
    input MCLK,
    input RESET,
    input [11:0] HPERIOD,
    input [11:0] DUTY,
    input [3:0] VOL,
    output reg [3:0] OUT
    );
    
    reg [11:0] CNT;
    
    assign OUT = OSC ? VOL : 12'd0;
    
    always @(posedge MCLK or posedge RESET)
    begin
        if (RESET)
        begin
            CNT <= 12'd0;
            OSC <= 1'b0;
        end
        else
        begin
			if (CNT)
			begin
                if (CNT == DUTY)
                    OSC <= 1'b1;		// Set sortie
                CNT <= CNT - 1'b1;	// Decrementer si > 0
            end
            else
            begin
                CNT <= HPERIOD;		// Reload
                OSC <= 1'b0;		// Reset sortie
            end
        end
    end
endmodule
Instancier 3 canaux:
reg [11:0] HPERIOD_A, HPERIOD_B, HPERIOD_C;
reg [11:0] DUTY_A, DUTY_B, DUTY_C;
reg [3:0] VOL_A, VOL_B, VOL_C;

wire [3:0] OUT_A, OUT_B, OUT_C;

channel CH_A(MCLK, RESET, HPERIOD_A, DUTY_A, VOL_A, OUT_A);
channel CH_B(MCLK, RESET, HPERIOD_B, DUTY_B, VOL_B, OUT_B);
channel CH_C(MCLK, RESET, HPERIOD_C, DUTY_C, VOL_C, OUT_C);
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