The ROMs (VSM)
The second circuit specially designed for the S&S is a type of ROM, the TMS6100, also called VSM or Voice Synthesis Memory. The name is a bit misleading because although this circuit has been designed to be paired with the TMS5100 synthesizer, it does not contain only voice data.
According to the IEEES article, it was the largest ROMs made at the time, with a capacity of 131072 bits, or 16kB internally organized as bytes.
These ROMs aren't like any parallel or serial memories found everywhere today, they have a special interface and pinout. The datasheet shows that the interface is like no other and that half of the pins are actually useless (see the picture of a cartridge).
First, there aren't two busses for address and data, but only a 4-bit one, which pins aren't numbered 0 to 3 but 1,2,4, and 8, which corresponds to the powers of 2. At the time it seems that this notation was preferred. The datasheet says that it is a multiplexed bus and two other pins called M0 and M1 are used to indicate a command.
Second, there is also a ROMCLK pin which might suggest that the circuit is completely synchronous. In reality it is not !
Here's what the M0 and M1 commands are:
||NOP, no operation
||"Read and branch" (never used in the S&S)
Let's take things step by step. To read data, we first have to first set the address. To address the whole 16ko, 14 bits would be needed, yet there is only a 4-bit bus. To set the address, at least 4 writes should be needed. However, the datasheet says that 5 writes are needed. This is the answer to the question of the absent Chip Select signal.
In fact, these ROMs have an internal address counter of not 14, but 18 bits. The 4 MSBs are used in place of a Chip Select.
When programmed, the ROM is attribued a 4 bits mask which will be compared with the 4 MSBs of the address counter, and the ROM will respond only if the two are identical.
For example, if the ROM's Chip Select mask is set to 0101 (5), it will only respond if the address is between 01 0100 0000 0000 0000 and (0x14000) 01 0111 1111 1111 1111 (0x17FFF). The whole point of this system is to be able to wire ROMs in parallel, to be seen as a continuous unique ROM.
In the UK S&S there are 2 ROMs in parallel, the first has its CS mask at 0000 and the second at 0001. If for example the addresd is 0x025A7, the 4 MSB will be 0000, and A13 ~ A0 will be 0x25A7. Since they are in parallel, all address counters ROMs on the bus are set to this address. The 4 MSB correspond to the first ROM's CS mask, so it will be the one which will respond. If the address is now 0x06B13, the 4 MSB will be 0001 and A13 ~ A0 will be 0x2B13, so the second ROM will respond.
This concept seems pretty special when accustomed to have a simple /CS signal to choose which ROM to talk to, but it allows to have many ROMs wired in parallel (up to 1111 = 16), with it beeing transparent to the processor and requiring no addtionnal address decoding logic
To set the address, we have to make 5 writes, to set 18 bits + 2 which are ignored. It is clear that the data is latched on the falling edge of ROMCLK ("A"). No ambiguity. However, what I discovered with the scope and which isn't shown in the chronogram, is that the command is executed only after receiving a NOP. As long as a NOP isn't received, the other falling edges of the clock on the same high state of M1 will do nothing.
This is important because the S&S program keeps M1 high during several periods of the clock !
After each write, an internal pointer advances 4 bits to point to the next ones in the address register. This pointer is reset to zero only after a bit read.
||Address bits set
Once the address is set, we can start reading data. For this, the datasheet says there are two choices: either by reading 4-bit words (using up the entire bus) or bit-by-bit (on the ADD8 line). Unfortunately, his is a factory-programmed option and the one chosen in the S&S ROMs is the bit-by-bit one.
This is where things get delicate, and almost made me go crazy.
One might expect that ADD8 becomes an output after a read command (M0 high) is validated on the falling edge of the clock, as to set the address.
This is indeed the case, but there are two details: the first is that the ROM requires a dummy read just after the address is set. It's only needed to load up the internal shift register. The fetching of all the other bits is done automatically after each actual read.
Once this dummy read done, we can begin reading the actual data. The second and most annoying detail is here: the read command is validated on the falling edge of the clock, but the response on ADD8 is done on the falling edge of ... I did not pay attention to this detail, as I was paying most attention to the chronogram in the synthesizer datasheet, which follows:
The address setting is very clear, we can see the five commands with the 20 bits loaded. The dummy read is also very clear, but reading the first bit is much less.
Indeed, it isn't very clear if ADD8 takes the value D0 on the falling edge of ROMCLK or M0...
This is a mistake that made me lose a lot of time and severely inflicted the results of my AVR based cartridge.